CUDA Design Rule Checking

Design Rule Checking (DRC) of semiconductor layouts is a massively independently parallel problem, and well suited for CUDA. As part of an Independent Study, my friend Jeremy Espenshade and I implemented DRC algorithms using CUDA and achieved approximately 25-30x speedup of the checking algorithm on a Tesla card from 2009.

Download:

/img/tools/cuda-design-rule-checking/design_rules.png
Tools  CUDA